Share
test resource partitioning for system-on-a-chip
Chandra,Iyengar,Chakrabarty (Author)
·
springer publishing map
· Physical Book
test resource partitioning for system-on-a-chip - chandra,iyengar,chakrabarty
Choose the list to add your product or create one New List
✓ Product added successfully to the Wishlist.
Go to My Wishlists
Origin: U.S.A.
(Import costs included in the price)
It will be shipped from our warehouse between
Tuesday, July 30 and
Tuesday, August 06.
You will receive it anywhere in United Kingdom between 1 and 3 business days after shipment.
Synopsis "test resource partitioning for system-on-a-chip"
test resource partitioning for system-on-a-chip is about test resource partitioning and optimization techniques for plug-and-play system-on-a-chip (soc) test automation. plug-and-play refers to the paradigm in which core-to-core interfaces as well as core-to-soc logic interfaces are standardized, such that cores can be easily plugged into virtual sockets on the soc design, and core tests can be plugged into the soc during test without substantial effort on the part of the system integrator. the goal of the book is to position test resource partitioning in the context of soc test automation, as well as to generate interest and motivate research on this important topic. soc integrated circuits composed of embedded cores are now commonplace. nevertheless, there remain several roadblocks to rapid and efficient system integration. test development is seen as a major bottleneck in soc design, and test challenges are a major contributor to the widening gap between design capability and manufacturing capacity. testing socs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. test resource partitioning for system-on-a-chip responds to a pressing need for a structured methodology for soc test automation. it presents new techniques for the partitioning and optimization of the three major soc test resources: test hardware, testing time and test data volume. test resource partitioning for system-on-a-chip paves the way for a powerful integrated framework to automate the test flow for a large number of cores in an soc in a plug-and-play fashion. the framework presented allows the system integrator to reduce test cost and meet short time-to-market requirements.
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
All books in our catalog are Original.
The book is written in English.
✓ Producto agregado correctamente al carro, Ir a Pagar.